Technical Field
The present invention relates to printed circuit board layout technology. More particularly, the present invention relates to a method and a system for virtual node layout of signals between a dynamic random-access memory (DRAM) and a central processing unit (CPU) on a printed circuit board.
Description of Related Art
In the design of signal lines on a printed circuit board (PCB), signal lines between components include many branch lines, and the length and symmetry of every branch line must meet certain requirements.
The present circuit layout software can merely calculate a pin-to-pin length between components. If a signal node exists between one component to another component, for example, a via or a T point (the design of a signal connection is like a “T”), then a layout engineer has to manually dispose virtual nodes provided by the software at the signal nodes for the circuit layout software to calculate lengths between the signal nodes and the component pins.
As the complexity of PCB design increases, disposing virtual nodes manually not only results in problems of poor quality resulting from human error, but efficiency is low. Thus, those skilled in the art have been endeavoring to devise a method for PCB layout that disposes virtual nodes automatically.